JPH0348658Y2 - - Google Patents
Info
- Publication number
- JPH0348658Y2 JPH0348658Y2 JP1980053840U JP5384080U JPH0348658Y2 JP H0348658 Y2 JPH0348658 Y2 JP H0348658Y2 JP 1980053840 U JP1980053840 U JP 1980053840U JP 5384080 U JP5384080 U JP 5384080U JP H0348658 Y2 JPH0348658 Y2 JP H0348658Y2
- Authority
- JP
- Japan
- Prior art keywords
- flop
- flip
- arithmetic control
- power supply
- counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Power Sources (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1980053840U JPH0348658Y2 (en]) | 1980-04-18 | 1980-04-18 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1980053840U JPH0348658Y2 (en]) | 1980-04-18 | 1980-04-18 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56156123U JPS56156123U (en]) | 1981-11-21 |
JPH0348658Y2 true JPH0348658Y2 (en]) | 1991-10-17 |
Family
ID=29648639
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1980053840U Expired JPH0348658Y2 (en]) | 1980-04-18 | 1980-04-18 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0348658Y2 (en]) |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5612888B2 (en]) * | 1972-05-26 | 1981-03-25 | ||
JPS5015430A (en]) * | 1973-06-08 | 1975-02-18 | ||
JPS5493333A (en) * | 1977-12-30 | 1979-07-24 | Ricoh Co Ltd | Controller having memory element in one bit unit |
-
1980
- 1980-04-18 JP JP1980053840U patent/JPH0348658Y2/ja not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS56156123U (en]) | 1981-11-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6141764A (en) | Method for initializing an electronic device using a dual-state power-on-reset circuit | |
US4812679A (en) | Power-on reset circuit | |
JPS62234418A (ja) | パワ−アツプリセツト回路 | |
US4983857A (en) | Power-up reset circuit | |
US4196362A (en) | Clear signal generator circuit | |
JPH0697429B2 (ja) | 低電圧阻止制御装置 | |
EP0549165A2 (en) | Power conserving integrated circuit | |
US5638330A (en) | Low dissipation initialization circuit, particularly for memory registers | |
JPH0348658Y2 (en]) | ||
KR100639759B1 (ko) | 파워-온 리셋 회로 | |
JPS6226604B2 (en]) | ||
JPH08298444A (ja) | 電源検出回路 | |
JPH1131956A (ja) | リセット信号発生回路 | |
JPH10107610A (ja) | 半導体集積回路 | |
JPS61178798A (ja) | モノリシツクromの保護回路 | |
JPH0224287Y2 (en]) | ||
JP2776093B2 (ja) | リセット回路 | |
JPH04162820A (ja) | 電源投入リセット回路 | |
JP2000165221A (ja) | 電源電圧監視回路 | |
KR100528526B1 (ko) | 오동작 방지회로 | |
JPH0352326A (ja) | パワーオンリセット回路 | |
KR900000486B1 (ko) | 씨모오스 시간 지연회로 | |
JP3022801B2 (ja) | ラッチアップ防止回路 | |
JP2845541B2 (ja) | リセット回路を有する電源供給回路 | |
JP4350854B2 (ja) | 制御対象の状態維持回路装置及び状態維持方法 |